Wednesday, February 24, 2010

myhdl

cool project converts python directly to vhdl or verilog. looks like it's under active development, with demo projects posted. if i ever need to use an fpga or cpld again, i know where to go.
and one of the examples uses the cypress fx2 usb controller chip, with references to other dsp interface projects (at 30 MB/s) including a 33khz adc fpga/fx2 microcontroller demo.

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